Design Verification Engineer

We are looking for an ASIC Verification Engineer to help advance cutting-edge chip designs utilizing 7nm and 5nm process technologies. This position entails verifying domain-specific processors for IAAS and smart-switch applications, using the P4 programming language to facilitate software-defined features while ensuring hard-wired performance. The role encompasses the development of sophisticated PCIe, networking, storage, and security virtualization services tailored for both public and private cloud markets.

Key Responsibilities

Establish verification testing strategies and create detailed plansCreate and implement test plans for unit, IP, subsystem, and SoC level verificationDesign SystemVerilog test benches that include stimulus, checkers, transactors/BFMs, assertions, and coverage pointsDetect issues in architecture, functionality, and performanceEnhance design verification methodologies and develop reusable verification frameworksAssist with verification efforts across module-level testing, full chip analysis, emulation, prototyping, silicon bring-up, manufacturing diagnostics, compilers, and shipping platform softwareCollaborate closely with micro-architecture and design teams

Required Skills & Experience

In-depth understanding of Computer ArchitecturePractical experience with UVM, SystemVerilog, C, and C++Familiarity with SystemVerilog simulators and waveform debugging toolsProven experience in developing and executing verification plans at the Unit, IP, Subsystem, and SoC levelsExperience in creating SystemVerilog test benches, including stimulus, checkers, transactors/BFMs, assertions, and coverage pointsStrong debugging and analytical skills in identifying bugsFamiliarity with design and verification tools such as VCS or equivalent simulation softwareExperience with debugging tools like Debussy/DVEExceptional debugging and problem-solving abilities